? semiconductor components industries, llc, 2002 august, 2002 rev. 7 1 publication order number: nths5441t1/d nths5441t1 power mosfet p-channel chipfet 3.9 amps, 20 volts features ? low r ds(on) ? higher efficiency extending battery life ? logic level gate drive ? miniature chipfet surface mount package applications ? power management in portable and batterypowered products; i.e., cellular and cordless telephones and pcmcia cards maximum ratings (t a = 25 c unless otherwise noted) rating symbol 5 secs steady state unit drainsource voltage v ds 20 v gatesource voltage v gs 12 v continuous drain current (t j = 150 c) (note 1) t a = 25 c t a = 85 c i d 5.3 3.8 3.9 2.8 a pulsed drain current i dm 20 a continuous source current (note 1) i s 2.1 1.1 a maximum power dissipation (note 1) t a = 25 c t a = 85 c p d 2.5 1.3 1.3 0.7 w operating junction and storage temperature range t j , t stg 55 to +150 c 1. surface mounted on 1 x 1 fr4 board. device package shipping ordering information nths5441t1 chipfet 3000/tape & reel g d s d d d d d 1 2 3 4 5 6 7 8 pin connections g s d pchannel mosfet chipfet case 1206a style 1 marking diagram a3 a3 = specific device code 3.9 amps 20 volts r ds(on) = 60 m 1 2 3 4 8 7 6 5 http://onsemi.com
nths5441t1 http://onsemi.com 2 thermal characteristics characteristic symbol typ max unit maximum junctiontoambient (note 2) t 5 sec steady state r thja 40 80 50 95 c/w maximum junctiontofoot (drain) steady state r thjf 15 20 c/w electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol test condition min typ max unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.6 1.2 v gatebody leakage i gss v ds = 0 v, v gs = 12 v 100 na zero gate voltage drain current i dss v ds = 16 v, v gs = 0 v 1.0 a v ds = 16 v, v gs = 0 v, t j = 85 c 5.0 onstate drain current (note 3) i d(on) v ds 5.0 v, v gs = 4.5 v 20 a drainsource onstate resistance (note 3) r ds(on) v gs = 3.6 v, i d = 3.7 a v gs = 4.5 v, i d = 3.9 a 0.050 0.046 0.06 v gs = 2.5 v, i d = 3.1 a 0.070 0.083 forward transconductance (note 3) g fs v ds = 10 v, i d = 3.9 a 12 mhos diode forward voltage (note 3) v sd i s = 1.1 a, v gs = 0 v 0.8 1.2 v dynamic (note 4) total gate charge q g v 10 v v 45v 11 22 nc gatesource charge q gs v ds = 10 v, v gs = 4.5 v, i d = 3.9 a 3.0 gatedrain charge q gd i d = 3 . 9 a 2.5 input capacitance c iss v 50vd v 0vd 710 pf output capacitance c oss v ds = 5.0 vdc, v gs = 0 vdc, f = 1.0 mhz 400 reverse transfer capacitance c rss f = 1 . 0 mhz 140 turnon delay time t d(on) 14 30 ns rise time t r v dd = 10 v, r l = 10 i d 10a v gen =45v 22 55 turnoff delay time t d(off) i d 1.0 a, v gen = 4.5 v, r g = 6 42 100 fall time t f r g 6 35 70 sourcedrain reverse recovery time t rr i f = 1.1 a, di/dt = 100 a/ s 30 60 2. surface mounted on 1 x 1 fr4 board. 3. pulse test: pulse width 300 s, duty cycle 2%. 4. guaranteed by design, not subject to production testing.
nths5441t1 http://onsemi.com 3 typical electrical characteristics 125 c 2.5 v 0 20 2.5 16 12 3 1.5 1 v ds , draintosource voltage (volts) i d, drain current (amps) 8 4 0 0.5 figure 1. onregion characteristics 0 20 16 1.5 12 12 8 4 0.5 0 2.5 3 figure 2. transfer characteristics v gs , gatetosource voltage (volts) 0 0.05 24 0.15 0.1 0 5 figure 3. onresistance versus gatetosource voltage v gs , gatetosource voltage (volts) r ds(on), draintosource resistance ( ) i d, drain current (amps) 21820 14 10 0.15 0.1 6 0.05 figure 4. onresistance versus drain current and gate voltage i d, drain current (amps) 50 0 25 25 1.4 1.2 1 0.8 0.6 50 125 100 figure 5. onresistance variation with temperature t j , junction temperature ( c) t j = 25 c v gs = 1.5 v 0.2 13 t j = 55 c i d = 3.9 a t j = 25 c 0.2 0 75 150 t j = 25 c v gs = 2.5 v i d = 3.9 a v gs = 4.5 v r ds(on), draintosource resistance (normalized) 2 2 v 3 v 3.5 v 5 v 4.5 v 4 v 25 c r ds(on), draintosource resistance ( ) 1.6 v gs = 3.6 v v gs = 4.5 v
nths5441t1 http://onsemi.com 4 typical electrical characteristics v gs 812 4 016 1200 900 600 300 0 20 v ds , draintosource voltage (volts) figure 6. capacitance variation c, capacitance (pf) 04 5 210 4 1 0 figure 7. gatetosource and draintosource voltage versus total charge q g , total gate charge (nc) v gs, gatetosource voltage (volts) t j = 25 c v gs = 0 c oss c iss c rss i d = 3.9 a t j = 25 c qt 1500 8 6 2 3 v ds, draintosource voltage (volts) 25 20 15 10 5 0 v ds q2 q1 0.0001 1 0.01 10 0.1 0.01 square wave pulse duration (sec) 0.1 1 0.001 figure 8. normalized thermal transient impedance, junctiontoambient duty cycle = 0.5 100 1000 normalized effective transient thermal impedance 0.2 single pulse 0.1 0.05 0.02 per unit base = r ja = 80 c/w t jm - t a = p dm z ja (t) surface mounted p dm t 1 t 2 duty cycle, d = t 1 /t 2 figure 9. diode forward voltage versus current 0.3 0.1 0.5 0.7 0.9 5 3 2 1 0 i s , source current (amps) v sd , sourcetodrain voltage (volts) v gs = 0 v t j = 25 c 4
nths5441t1 http://onsemi.com 5 80 mil 26 28 18 mil 25 mil figure 10. figure 11. 80 mil 26 28 68 mil mil mil mil mil basic pad patterns the basic pad layout with dimensions is shown in figure 11. this is sufficient for low power dissipation mosfet applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. the minimum recommended pad pattern shown in figure 10 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the confines of the basic footprint. the drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). this will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. the addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further.
nths5441t1 http://onsemi.com 6 package dimensions chipfet ? case 1206a03 issue d b s c d g l a 1234 8765 m j k 1 2 3 4 8 7 6 5 dim min max min max inches millimeters a 2.95 3.10 0.116 0.122 b 1.55 1.70 0.061 0.067 c 1.00 1.10 0.039 0.043 d 0.25 0.35 0.010 0.014 g 0.65 bsc 0.025 bsc j 0.10 0.20 0.004 0.008 k 0.28 0.42 0.011 0.017 l 0.55 bsc 0.022 bsc m 5 nom s 1.80 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. mold gate burrs shall not exceed 0.13 mm per side. 4. leadframe to molded body offset in horizontal and vertical shall not exceed 0.08 mm. 5. dimensions a and b exclusive of mold gate burrs. 6. no mold flash allowed on the top and bottom lead surface. 7. 1206a-01 and 1206a-02 obsolete. new standard is 1206a-03. 0.05 (0.002) 5 nom style 1: pin 1. drain 2. drain 3. drain 4. gate 5. source 6. drain 7. drain 8. drain 2.00 0.072 0.080
nths5441t1 http://onsemi.com 7 notes
nths5441t1 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 291 kamimeguro, meguroku, tokyo, japan 1530051 phone : 81357733850 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nths5441t1/d chipfet is a trademark of vishay siliconix literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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